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20 v, 500 ma, low noise, cmos ldo data sheet adp7104 rev. b information furnished by analog devices is believed to be accurate and reliable. however, no responsibility is assumed by analog devices for its use, nor for any infringements of patents or other rights of third parties that may result from its use. specifications subject to change without notice. no license is granted by implication or otherwise under any patent or patent rights of analog devices. trademarks and registered tradema rks are the property of their respective owners. one technology way, p.o. box 9106, norwood, ma 02062 - 9106, u.s.a. tel: 781.329.4700 www.analog.com fax: 781.461.3113 ? 2011 C 2012 anal og devices, inc. all rights reserved. features input voltage range: 3.3 v to 20 v maximum output current: 500 ma low n oise: 15 v rms for fixed output versions psrr p erformance of 60 db at 10 khz , v out = 3.3 v reverse current protection low dropout voltage: 35 0 mv at 500 ma initial accuracy: 0.8 % accuracy over line, load, and temperature: ? 2 % /+1 % low quiescent curre nt ( v in = 5 v ) , i gnd = 900 a with 500 ma load low shutdown current: <4 0 a at v in = 12 v , s table with small 1 f ceramic output capacitor 7 fixed output voltage options: 1.5 v, 1.8 v , 2.5 v , 3 v , 3.3 v , 5 v , and 9 v adjustable o utput from 1.22 v to v in ? v do foldback current limit and thermal overload protection user programmable precision u v lo / e nable power - good indicator 8 - lead lfcsp and 8 - l ead soic package s applications regulation to noise sensitive applications: adc, dac circu its, precision amplifiers, high frequency oscillators, clocks , and plls communications and infrastructure medical and healthcare industrial and instrumentation typical application circuit s v out = 5v v in = 8v pg vout vin pg gnd sense en/ uvlo 100k ? 100k ? 100k ? cout 1f cin 1f on off + + 09507-001 figure 1. adp7104 with fixed output voltage, 5 v v out = 5v v in = 8v pg vout vin pg gnd adj en/ uvlo 100k ? 100k ? 100k ? cout 1f cin 1f on off + + 13k ? 40.2k ? 09507-002 figure 2. adp7104 with adjustable output voltage, 5 v general description the adp7104 is a cmos, low dropout linear regulator that operates from 3.3 v to 20 v and provide s up to 500 ma of output current. this high input voltage ldo is ideal for regulation of high performance analog and mixed signal circuits operating from 19 v t o 1.22 v rails. using an advanced proprietary architecture, it provides high power supply rejection, low noise, and achieves excellent line and load transient response with just a small 1 f ceramic output capacitor. the adp7104 is available in seven fixed output voltage options and an adjustable version, which allows output voltages that range from 1.22 v to v in ? v do via an external feedback divider. the adp710 4 output noise voltage is 15 v rms and is inde - pendent of the output voltage. a digital power - good output allows power system monitors to check the health of the output voltage. a user programmable precision undervoltage lockout function facilitates sequ encing of multiple power supplies. the adp7104 is available in 8 - lead, 3 mm 3 mm lfcsp and 8 - lead soic packages. the lfcsp offers a very compact solution and also provides excellent thermal performance for applications requiring up to 500 ma of output current in a small, low - profile footprint.
adp7104 data sheet rev. b | page 2 of 28 table of contents features .............................................................................................. 1 applications ....................................................................................... 1 typical application circuits ............................................................ 1 general description ......................................................................... 1 revision history ............................................................................... 2 specifications ..................................................................................... 3 input and output capacitor, recommended specifications .. 4 absolute maximum ratings ............................................................ 5 thermal data ................................................................................ 5 thermal resistance ...................................................................... 5 esd caution .................................................................................. 5 pin configurations and function descriptions ........................... 6 typical performance characteristics ..............................................7 theory of operation ...................................................................... 16 applications information .............................................................. 17 capacitor selection .................................................................... 17 programable undervoltage lockout (uvlo ) ........................... 18 power - good feature .................................................................. 19 noise reduction of the adjustable adp7104 ............................ 19 current limit and thermal overload protection ................. 20 thermal considerations ............................................................ 20 printed circuit board layout considerations ............................ 23 outline dimensions ....................................................................... 24 o rdering guide .......................................................................... 25 revision history 3/12 rev. a to rev. b changes to figure 6 6 ...................................................................... 18 11/ 11 rev. 0 to rev. a changed low dropout voltage from 200 mv to 350 mv .......... 1 changes to dropout voltage parameter ........................................ 3 10/ 1 1 revision 0: initial ver sion
data sheet adp7104 rev. b | page 3 of 28 specifications v in = (v out + 1 v ) or 3.3 v (whichever is greater), en = v in , i out = 10 ma, c in = c out = 1 f, t a = 25c , unless otherwise noted. table 1 . parameter symbol conditions min typ max unit input voltage range v in 3. 3 20 v operating supply current i gnd i out = 100 a, v in = 10 v 400 a i out = 100 a, v in = 10 v, t j = ?40 c to + 125 c 900 a i out = 10 ma, v in = 10 v 450 a i out = 10 ma, v in = 10 v, t j = ?40 c to + 125 c 1050 a i out = 300 ma, v in = 10 v 750 a i out = 300 ma, v in = 10 v, t j = ?40 c to + 125 c 1400 a i out = 500 ma, v in = 10 v 900 a i out = 500 ma, v in = 10 v, t j = ? 40 c to + 125 c 1600 a shutdown current i gnd - sd en = gnd, v in = 12 v 40 50 a en = gnd, v in = 12 v , t j = ?40 c to + 125 c 75 a input reverse current i rev - input en = gnd, v in = 0 v, v out = 20 v 0.3 a en = gnd, v in = 0 v, v out = 20 v, t j = ?40 c to + 125 c 5 a output voltage accuracy fixed output voltage accuracy v out i out = 10 ma C 0.8 + 0.8 % 1 ma < i out < 500 ma, v in = (v out + 1 v) to 20 v, t j = ?40 c to + 125 c C 2 + 1 % adjustable output voltage accuracy v adj i out = 10 ma 1.21 1.22 1.23 v 1 ma < i out < 500 ma, v in = (v out + 1 v) to 20 v, t j = ?40 c to + 125 c 1.196 1.232 v li ne regulation ? v out /?v in v in = (v out + 1 v) to 20 v, t j = ?40 c to + 125 c ? 0.015 + 0.015 %/v load regulation 1 ? v out /?i out i out = 1 ma to 500 ma 0.2 %/a i out = 1 ma to 500 ma, t j = ?40 c to + 125 c 0.75 %/a adj input bias current adj i- bias 1 ma < i out < 500 ma , v in = (v out + 1 v) to 20 v, adj connected to vout 10 na sense input bias current sense i- bias 1 ma < i out < 500 ma , v in = (v out + 1 v) to 20 v, sense connected to vout, v out = 1.5 v 1 a dropout voltage 2 v dropout i out = 10 ma 20 mv i out = 10 ma, t j = ?40 c to + 125 c 40 mv i out = 150 ma 100 mv i out = 150 ma, t j = ?40 c to + 125 c 175 mv i out = 3 00 ma 200 mv i out = 3 00 ma, t j = ?40 c to + 125 c 325 mv i out = 500 ma 350 mv i out = 500 ma, t j = ?40c to +125 c 550 mv start - up time 3 t start - up v out = 5 v 1000 s current - limit threshold 4 i limit 625 775 1000 ma pg output logic level pg output logic high pg high i oh < 1 a 1.0 v pg output logic low pg low i ol < 2 ma 0.4 v pg output threshold output voltage falling pg fal l ? 9.2 % output voltage rising pg rise ? 6.5 % thermal shutdown thermal shutdown threshold ts sd t j rising 150 c thermal shutdown hysteresis ts sd - hys 15 c
adp7104 data sheet rev. b | page 4 of 28 parameter symbol conditions min typ max unit programmable en/uvlo uvlo threshold r ising uvlo rise 3.3 v v in 20 v, t j = ?40 c to + 125 c 1.18 1.23 1.28 v uvlo threshold falling uvlo fal l 3.3 v v in 20 v, t j = ?40c to +125c, 10 k in series with the e nable pin 1.13 v uvlo hysteresis current uvlo hys v en > 1.25 v, t j = ?40c to +1 25c 7.5 9.8 12 a enable pull -d own current i en - in en = v in 500 na start threshold v start t j = ?40 c to + 125 c 3.2 v shutdown threshold v shutdown t j = ?40 c to + 125 c 2.45 v hysteresis 250 mv output noise out noise 10 hz to 100 khz, v in = 5.5 v, v out = 1.8 v 15 v rms 10 hz to 100 khz, v in = 6.3 v, v out = 3.3 v 15 v rms 10 hz to 100 khz, v in = 8 v, v out = 5 v 15 v rms 10 hz to 100 khz, v in = 12 v, v out = 9 v 15 v rms 10 hz to 100 khz, v in = 5.5 v, v out = 1.5 v , adjusta ble mode 18 v rms 10 hz to 100 khz, v in = 12 v, v out = 5 v, adjustable mode 30 v rms 10 hz to 100 khz, v in = 20 v, v out = 15 v , adjustable mode 65 v rms power supply rejection ratio psrr 100 khz, v in = 4.3 v, v out = 3.3 v 50 db 100 kh z, v in = 6 v, v out = 5 v 50 db 10 khz, v in = 4.3 v, v out = 3.3 v 60 db 10 khz, v in = 6 v, v out = 5 v 60 db 100 khz, v in = 3.3 v , v out = 1.8 v, adjustable mode 50 db 100 khz, v in = 6 v, v out = 5 v, adjustable mode 60 db 100 khz, v in = 16 v, v out = 15 v, adjustable mode 60 db 10 khz, v in = 3.3 v, v out = 1.8 v, adjustable mode 60 db 10 khz, v in = 6 v, v out = 5 v, adjustable mode 80 db 10 khz, v in = 16 v, v out = 15 v, adjustable mode 80 db 1 based on an end - point calculation using 1 ma and 30 0 ma loads. see figure 6 for typical load re gulation performance for loads less than 1 ma. 2 dropout voltage is defined as the input - to - output voltage differential when the i nput voltage is set to the nominal output voltage. this applies only for output voltages above 3.0 v. 3 start - up time is defined as the time between the rising edge of en to vout being at 90 % of its nominal value. 4 current limit threshold is defined as th e current at which the output voltage drops to 90% of the specified typical value. for example, the current limit for a 5 . 0 v output voltage is defined as the current that causes the output voltage to drop to 90% of 5.0 v, or 4.5 v. input and output cap acitor, recommended specific ations table 2 . parameter symbol conditions min typ max unit m inimum i nput and o utput c apacitance 1 c min t a = ?40 c to + 125 c 0. 7 f c apacitor esr r esr t a = ?40 c to + 125 c 0 . 001 0.2 1 the minimum input and output capacitance should be greater than 0.7 f over the full range of operating conditions. the full range of operating con ditions in the application must be considered during device selection to ensure that the minimum capacitance specification is met. x7r and x5r type capacitors are recommended; y5v and z5u capacitors are not recommended for use with any ldo.
data sheet adp7104 rev. b | page 5 of 28 absolute maxim um ratings table 3 . parameter rating vin to gnd ? 0.3 v to + 22 v vout to gnd ? 0.3 v to +20 v en /uvlo to gnd ? 0.3 v to v in pg to gnd ? 0.3 v to v in sense/adj to gnd ? 0.3 v to v out storage temperature range ? 65 c to + 150 c oper ating junction temperature range ? 40 c to + 125 c operating ambient temperature range ? 40 c to + 85 c soldering conditions jedec j - std -020 stresses above those listed under absolute maximum ratings may cause permanent damage to the device. this is a stres s rating only and functional operation of the device at these or any other conditions above those indicated in the operational section of this specification is not implied. exposure to absolute maximum rating conditions for extended periods may affect devi ce reliability. thermal data absolute maximum ratings apply individually only, not in combination. the adp7104 can be damaged when the junction temperature limit is exceeded. monitoring ambient temperature doe s not guarantee that t j is within the specified temperature limits. in applications with high power dissipation and poor thermal resistance, the maximum ambient temperature may have to be derated. in applications with moderate power dissipation and low pc b thermal resistance, the maximum ambient temperature can exceed the maximum limit as long as the junction temperature is within specification limits. the junction temperature (t j ) of the device is dependent on the ambient temperature (t a ), the power dissi pation of the device (p d ), a nd the junction - to - ambient thermal resistance of the package ( ja ). maximum junction temperature (t j ) is calculated from the ambient temperature (t a ) and power dissipation (p d ) using the formula t j = t a + ( p d ja ) junction - t o - ambient thermal resistance ( ja ) of the package is based on modeling and calculation using a 4 - layer board. the junction - to - ambient thermal resistance is highly dependent on the application and board layout. in applications where high maximum power dissi pation exists, close attention to thermal board design is required. the value of ja may vary, depending on pcb material, layout, and environmental conditions. the specified values of ja are based on a 4 - layer, 4 in. 3 in. circuit board. see jesd51 - 7 an d jesd51 - 9 for detailed information on the board construction. for additional information, see the an - 617 application note, microcsp ? wafer level chip scale package , available at www.analog.com . jb is the junction - t o - board thermal characterization parameter with units of c/w. the packages jb is based on modeling and calculation using a 4 - layer board. the jesd51 - 12, guidelines for reporting and using electronic package thermal information , states that thermal chara cterization parameters are not the same as thermal resistances. jb measures the component power flowing through multiple thermal paths rather than a single path as in thermal resistance, jb . therefore, jb thermal paths include convection from the top of the package as well as radiation from the package, factors that make jb more useful in real - world applications. maximum junction temperature (t j ) is calculated from the board temperature (t b ) and power dissipation (p d ) using the formula t j = t b + ( p d jb ) see jesd51 - 8 and jesd51 - 12 for more detailed information about jb . thermal resistance ja and jb are specified for the worst - case conditions, that is, a device soldered in a circuit board for surface - mount packages . jc is a parameter for surface - mo unt packages with top mounted heatsinks. jc is presented here for reference only. table 4 . thermal resistance package type ja jc jb unit 8 - lead lfcsp 40.1 27.1 17.2 c/w 8 - lead soic 48.5 58.4 31.3 c/w esd caution
adp7104 data sheet rev. b | page 6 of 28 p in configurations and function descrip tions notes 1. nc = no connec t . do not connect t o this pin. 2. it is highly recommended that the exposed pad on the bottom of the package be connected to the ground plane on the board. 3 gnd 4 nc 1 vout 2 sense/adj 6 gnd 5 en/uvlo 8 vin 7 pg adp7104 t op view (not to scale) 09507-003 figure 3. lfcsp package notes 1. nc = no connec t . do not connect t o this pin. 2. it is highly recommended that the exposed pad on the bottom of the package be connected to the ground plane on the board. vout 1 sense/adj 2 gnd 3 nc 4 vin 8 pg 7 gnd 6 en/uvlo 5 ad p7104 top view (not to scale) 09507-004 figure 4. narrow body soic package table 5 . pin function descriptions pin no. mnemonic description 1 vo ut regulated output voltage. bypass vout to gnd with a 1 f or greater capacitor. 2 sense/adj sense (sense). measures the actual output voltage at the load and feeds it to the error amplifier. connect sense as close as possible to the load to minimize the effect of ir drop between the regulator output and the load. this function applies to fixed voltages only. adjust input (adj). an external resistor divider sets the output voltage. this function applies to adjustable voltages only. 3 gnd ground. 4 nc do not connect to this pin. 5 en/uvlo enable input (en). drive en high to turn on the regulator; drive en low to turn off the regulator. for automatic startup, connect en to vin. programmable undervoltage lockout (uvlo). when the programmable uvlo function is used, the upper and lower thresholds are determined by the programming resistors. 6 gnd ground. 7 pg power good. this open - drain output requires an external pull - up resistor to vin or vout. if the part is in shutdown, current limit, thermal shutdown, or falls below 90% of the nominal output voltage, pg immediately transitions low. if the power - good function is not used, the pin may be left open or connected to ground. 8 vin regulator input supply. bypass vin to gnd with a 1 f or greater capacitor. epad exposed pad. exposed paddle on the bottom of the package. the epad enhances thermal performance and is electrically connected to gnd inside the package. it is highly recommended that the epad be connected to the ground plane on the board.
data sheet adp7104 rev. b | page 7 of 28 typical performance characte ristics v in = 7. 5 v, v out = 5 v , i out = 1 0 ma , c in = c out = 1 f , t a = 25c, unless otherwise noted . 3.25 3.27 3.29 3.31 3.33 3.35 v out (v) load = 100a load = 1ma load = 10ma load = 100ma load = 300ma load = 500ma ?40 c ?5 c 25 c 85 c 125 c t j ( c ) 09507-005 figure 5 . output voltage vs. junction temperature 3.25 3.27 3.29 3.31 3.33 3.35 0.1 1 10 100 1000 v out (v) i load (ma) 09507-006 figure 6 . output voltage v s. load current 3.25 3.27 3.29 3.31 3.33 3.35 4 6 8 10 12 14 16 18 20 v out (v) v in (v) load = 100 a load = 1ma load = 10ma load = 100ma load = 300ma load = 500ma 09507-007 figure 7 . output voltage vs. input voltage 0 200 400 600 800 1000 1200 ground current ( a) ?40 c ?5 c 25 c 85 c 125 c t j ( c ) load = 100 a load = 1ma load = 10ma load = 100ma load = 300ma load = 500ma 09507-008 figure 8 . ground current vs. junction temperature 0 100 200 300 400 500 600 700 800 0.1 1 10 100 1000 i load (ma) ground current ( a) 09507-009 figure 9 . ground current vs. load current 0 200 400 600 800 1000 1200 4 6 8 10 12 14 16 18 20 ground current ( a) v in (v) load = 100 a load = 1ma load = 10ma load = 100ma load = 300ma load = 500ma 09507-010 figure 10 . ground current vs. input voltage
adp7104 data sheet rev. b | page 8 of 28 shutdown current ( a) 0 20 40 60 80 100 120 140 160 ?50 ?25 0 25 50 75 100 125 temper a ture (c) 3.3v 4.0v 6.0v 8.0v 12.0v 20.0v 09507-0 1 1 figure 11 . shutdown current vs. temperature at various input voltages 0 50 100 150 200 250 300 350 1 10 100 1000 dropout (mv) i load (ma) v out = 3.3v t a = 25c 09507-012 figure 12 . dropout voltage vs. load current 2.7 2.8 2.9 3.0 3.1 3.2 3.3 3.4 3.1 3.2 3.3 3.4 3.5 3.6 3.7 v out (v) v in (v) load = 5ma load = 10ma load = 100ma load = 200ma load = 300ma load = 500ma 09507-013 figure 13 . output voltage vs. input voltage (in dropout) 0 200 400 600 800 1000 1200 1400 3.1 3.2 3.3 3.4 3.5 3.6 3.7 ground current ( a) v in (v) load = 5ma load = 10ma load = 100ma load = 200ma load = 300ma load = 500ma 09507-014 figure 14 . ground current vs. input voltage (in dropout) 4.95 4.96 4.97 4.98 4.99 5.00 5.01 5.02 5.03 5.04 5.05 v out (v) load = 100a load = 1ma load = 10ma load = 100ma load = 300ma load = 500ma ?40 c ?5 c 25 c 85 c 125 c t j ( c ) 09507-015 figure 15 . output voltage vs. junction temperature, v out = 5 v 4.95 4.96 4.97 4.98 4.99 5.00 5.01 5.02 5.03 5.04 5.05 0.1 1 10 100 1000 v out (v) i load (ma) 09507-016 figure 16 . output voltage vs. load current, v out = 5 v
data sheet adp7104 rev. b | page 9 of 28 4.95 4.96 4.97 4.98 4.99 5.00 5.01 5.02 5.03 5.04 5.05 6 8 10 12 14 16 18 20 v out (v) v in (v) load = 100 a load = 1ma load = 10ma load = 100ma load = 300ma load = 500ma 09507-017 figure 17 . output voltage vs. input voltage, v out = 5 v 0 100 200 300 400 500 600 700 800 900 1000 25c 85c 125c ground current ( a) t j (c) ?40c ?5c load = 100 a load = 1ma load = 10ma load = 100ma load = 300ma 09507- 1 18 figure 18 . ground current vs. junction temperature, v out = 5 v 0 100 200 300 400 500 600 700 0.1 1 10 100 1000 ground current ( a) i load (ma) 09507- 1 19 figure 19 . ground current vs. load current, v out = 5 v 0 50 100 150 200 250 300 1 10 100 1000 dropout (mv) i load (ma) v out = 5v t a = 25c 09507-018 figure 20 . dropout voltage vs. load current, v out = 5 v 4.55 4.60 4.65 4.70 4.75 4.80 4.85 4.90 4.95 5.00 5.05 4.8 4.9 5.0 5.1 5.2 5.3 5.4 v out (v) v in (v) load = 5ma load = 10ma load = 100ma load = 200ma load = 300ma load = 500ma 09507-019 figure 21 . output voltage vs. input voltage (in dropout) ?500 0 500 1000 1500 2000 2500 4.80 4.90 5.00 5.10 5.20 5.30 5.40 ground current ( a) v in (v) load = 5ma load = 10ma load = 100ma load = 200ma load = 300ma load = 500ma 09507-020 figure 22 . ground current vs. input voltage (in dropout), v out = 5 v
adp7104 data sheet rev. b | page 10 of 28 1.75 1.77 1.79 1.81 1.83 1.85 v out (v) load = 100 a load = 1ma load = 10ma load = 100ma load = 300ma load = 500ma ?40 c ?5 c 25 c 85 c 125 c t j ( c ) 09507-021 figure 23 . output voltage vs. junction temperature, v out = 1.8 v v out (v) 1.75 1.77 1.79 1.81 1.83 1.85 0.1 1 10 100 1000 i load (ma) 09507-022 figure 24 . output voltage vs. load current, v out = 1.8 v 1.75 1.77 1.79 1.81 1.83 1.85 2 4 6 8 10 12 14 16 18 20 v out (v) v in (v) load = 100 a load = 1ma load = 10ma load = 100ma load = 300ma load = 500ma 09507-023 figure 25 . output voltage vs. input voltage, v out = 1.8 v 0 100 200 300 400 500 600 700 800 900 25c 85c 125c ground current ( a) t j (c) ?40c ?5c load = 100 a load = 1ma load = 10ma load = 100ma load = 300ma 09507-126 figure 26 . ground current vs. junction temperature, v out = 1.8 v 0 100 200 300 400 500 600 700 0.1 1 10 100 1000 ground current ( a) i load (ma) 09507-127 figure 27 . ground current vs. load curre nt, v out = 1.8 v 0 200 400 600 800 1000 1200 2 4 6 8 10 12 14 16 18 20 ground current ( a) v in (v) load = 100 a load = 1ma load = 10ma load = 100ma load = 300ma load = 500ma 09507-024 figure 28 . ground current vs. input voltage, v out = 1.8 v
data sheet adp7104 rev. b | page 11 of 28 4.98 4.99 5.00 5.01 5.02 5.03 5.04 5.05 5.06 5.07 5.08 v out (v) load = 100a load = 1ma load = 10ma load = 100ma load = 300ma load = 500ma ?40 c ?5 c 25 c 85 c 125 c t j ( c ) 09507-025 figure 29 . output voltage vs. junction temperature, v out = 5 v, adjustable 4.98 4.99 5.00 5.01 5.02 5.03 5.04 5.05 5.06 5.07 5.08 0.1 1 10 100 1000 v out (v) i load (ma) 09507-026 figure 30 . output v oltage vs. load current, v out = 5 v, adjustable 4.98 4.99 5.00 5.01 5.02 5.03 5.04 5.05 5.06 5.07 5.08 6 8 10 12 14 16 18 20 v out (v) v in (v) load = 100a load = 1ma load = 10ma load = 100ma load = 300ma load = 500ma 09507-027 figure 31 . output voltage vs. input voltage, v out = 5 v, adjustable 0 0.5 1.0 1.5 2.0 ?40 ?20 0 20 40 60 80 100 120 140 i out shutdown current ( a) temper a ture (c) 3.3v 4v 5v 6v 8v 10v 12v 15v 18v 20v 09507-054 figure 32 . reverse input current vs. temperature, v in = 0 v, different voltages on v out ?100 ?90 ?80 ?70 ?60 ?50 ?40 ?30 ?20 ?10 0 10 100 1k 10k 100k 1m 10m psrr (db) frequenc y (hz) load = 500ma load = 300ma load = 100ma load = 10ma load = 1ma 09507-028 figure 33 . power supply rejection ratio vs. frequency, v out = 1.8 v, v in = 3.3 v ?100 ?90 ?80 ?70 ?60 ?50 ?40 ?30 ?20 ?10 0 10 100 1k 10k 100k 1m 10m psrr (db) frequenc y (hz) 09507-029 load = 500ma load = 300ma load = 100ma load = 10ma load = 1ma figure 34 . power supply rejection ratio vs. frequency, v out = 3.3 v, v in = 4.8 v
adp7104 data sheet rev. b | page 12 of 28 ?100 ?90 ?80 ?70 ?60 ?50 ?40 ?30 ?20 ?10 0 10 100 1k 10k 100k 1m 10m psrr (db) frequenc y (hz) 09507-030 load = 500ma load = 300ma load = 100ma load = 10ma load = 1ma figure 35 . power supply rejection ratio vs. frequency, v out = 3.3 v, v in = 4.3 v ?100 ?90 ?80 ?70 ?60 ?50 ?40 ?30 ?20 ?10 0 10 100 1k 10k 100k 1m 10m psrr (db) frequenc y (hz) 09507-031 load = 500ma load = 300ma load = 100ma load = 10ma load = 1ma figure 36 . power supply rejection ratio vs. frequency, v ou t = 3.3 v, v in = 3.8 v ?100 ?90 ?80 ?70 ?60 ?50 ?40 ?30 ?20 ?10 0 psrr (db) frequenc y (hz) 10 100 1k 10k 100k 1m 10m load = 500ma load = 300ma load = 100ma load = 10ma load = 1ma 09507-032 figure 37 . power supply rejection rat io vs. frequency, v out = 5 v, v in = 6.5 v ?100 ?90 ?80 ?70 ?60 ?50 ?40 ?30 ?20 ?10 0 psrr (db) frequenc y (hz) 10 100 1k 10k 100k 1m 10m 09507-033 load = 500ma load = 300ma load = 100ma load = 10ma load = 1ma figure 38 . power supply rejection ratio vs. frequency, v out = 5 v, v in = 6 v ?100 ?90 ?80 ?70 ?60 ?50 ?40 ?30 ?20 ?10 0 psrr (db) 10 100 1k 10k 100k 1m 10m frequenc y (hz) 09507-034 load = 500ma load = 300ma load = 100ma load = 10ma load = 1ma figure 39 . power supply rejection ratio vs. frequency, v out = 5 v, v in = 5.5 v ?100 ?90 ?80 ?70 ?60 ?50 ?40 ?30 ?20 ?10 0 psrr (db) 10 100 1k 10k 100k 1m 10m frequenc y (hz) 09507-035 load = 500ma load = 300ma load = 100ma load = 10ma load = 1ma figure 40 . power supply rejection ratio vs. frequency, v out = 5 v, v in = 5.3 v
data sheet adp7104 rev. b | page 13 of 28 ?100 ?90 ?80 ?70 ?60 ?50 ?40 ?30 ?20 ?10 0 psrr (db) 10 100 1k 10k 100k 1m 10m frequenc y (hz) 09507-036 load = 500ma load = 300ma load = 100ma load = 10ma load = 1ma figure 41 . power supply rejection ratio vs. frequency, v out = 5 v, v in = 5.2 v ?100 ?90 ?80 ?70 ?60 ?50 ?40 ?30 ?20 ?10 0 psrr (db) 10 100 1k 10k 100k 1m 10m frequenc y (hz) 09507-037 load = 500ma load = 300ma load = 100ma load = 10ma load = 1ma figure 42 . power supply rejection ratio vs. frequency, v out = 5 v, v in = 6 v adjustable ?100 ?90 ?80 ?70 ?60 ?50 ?40 ?30 ?20 ?10 0 psrr (db) 10 100 1k 10k 100k 1m 10m frequenc y (hz) 09507-038 load = 500ma load = 300ma load = 100ma load = 10ma load = 1ma figure 43 . power supply rejection ratio vs . frequency , v out = 5 v , v in = 6 v adjustable with noise reduction circuit ?100 ?90 ?80 ?70 ?60 ?50 ?40 ?30 ?20 ?10 0 0 0.25 0.50 0.75 1.00 1.25 1.50 psrr (db) headroom vo lt age (v) 09507-039 load = 500ma load = 300ma load = 100ma load = 10ma load = 1ma figure 44 . power supply rejection ratio vs. headroom voltage, 100 hz, v out = 5 v ?100 ?90 ?80 ?70 ?60 ?50 ?40 ?30 ?20 ?10 0 0 0.25 0.50 0.75 1.00 1.25 1.50 psrr (db) headroom vo lt age (v) 09507-040 load = 500ma load = 300ma load = 100ma load = 10ma load = 1ma figure 45 . power supply rejection ratio vs. headroom voltage, 1 khz , v out = 5 v ?100 ?90 ?80 ?70 ?60 ?50 ?40 ?30 ?20 ?10 0 0 0.25 0.50 0.75 1.00 1.25 1.50 psrr (db) headroom vo lt age (v) 09507-041 load = 500ma load = 300ma load = 100ma load = 10ma load = 1ma figure 46 . power supply rejection ratio vs. headroom voltage, 10 khz , v out = 5 v
adp7104 data sheet rev. b | page 14 of 28 ?100 ?90 ?80 ?70 ?60 ?50 ?40 ?30 ?20 ?10 0 0 0.25 0.50 0.75 1.00 1.25 1.50 psrr (db) headroom vo lt age (v) load = 500ma load = 300ma load = 100ma load = 10ma load = 1ma 09507-042 figure 47 . power supply rejection ratio vs. headroom voltage, 100 khz , v out = 5 v 5 0 10 15 20 25 30 0.01 0.001 0.0001 0.00001 0.1 1 noise ( v rms) load current (a) 3.3v 1.8v 5v 5v adj 5v adj nr 09507-043 figure 48 . output noise vs. load current and output voltage, c out = 1 f frequenc y (hz) 0.01 0.1 1 10 10 100 1k 10k 100k noise ( v/ hz) 3.3v 5v 5v adj 5v adj nr 09507-044 figure 49 . output noise spectral density, i load = 10 ma, c out = 1 f ch2 50mv ch1 500ma m 20 s a ch1 270m a 1 2 t 10% ? load current output voltage 09507-045 b w b w figure 50 . load transient response, c in , c out = 1 f, i load = 1 ma to 500 ma , v out = 1.8 v, v in = 5 v ch2 50mv ch1 500m a m 20 s a ch1 280m a 1 2 t 10.2% ? load current output voltage 09507-046 b w b w figure 51 . load transient response, c in , c out = 1 f, i load = 1 ma to 500 ma , v out = 3.3 v, v in = 5 v ch2 50mv ch1 500m a m 20 s a ch1 300m a 1 2 t 10.2% ? load current output voltage 09507-047 b w b w figure 52 . load transient response, c in , c out = 1 f, i load = 1 ma to 500 ma , v out = 5 v, v in = 7 v
data sheet adp7104 rev. b | page 15 of 28 ch2 10mv ch1 1v m 4 s a ch4 1.56v 1 2 t 9.8% load current output voltage 09507-048 b w b w figure 53 . line transient response, c in , c out = 1 f, i load = 5 00 ma, v out = 1.8 v ch2 10mv ch1 1v m 4 s a ch4 1.56v 1 2 t 9.8% load current output voltage 09507-049 b w b w figure 54 . line transient response, c in , c out = 1 f, i load = 5 00 ma, v out = 3.3 v ch2 10mv ch1 1v m 4 s a ch4 1.56v 1 2 t 9.8% load current output voltage 09507-050 b w b w figure 55 . line transient response, c in , c out = 1 f, i load = 5 00 ma, v out = 5 v 1 2 load current output voltage 09507-051 ch2 10mv ch1 1v m 4 s a ch4 1.56v t 9.8% b w b w figure 56 . line transient response, c in , c out = 1 f, i load = 1 ma, v out = 1.8 v 1 2 load current output voltage 09507-052 ch2 10mv ch1 1v m 4 s a ch4 1.56v t 9.8% b w b w figure 57 . line transient response, c in , c out = 1 f, i load = 1 ma, v out = 3.3 v ch2 10mv ch1 1v m 4 s a ch4 1.56v 1 2 t 9.8% load current output voltage 09507-053 b w b w figure 58 . line transient response, c in , c out = 1 f, i load = 1 ma, v out = 5 v
adp7104 data sheet rev. b | page 16 of 28 theory of operation the adp7104 is a low quiescent current, lo w - dropout linear regulat or that operates from 3.3 v to 20 v and provide s up to 500 ma of output current. drawing a low 1 m a of quiescent current (typical) at full load makes the adp7104 ideal for battery - opera ted portable equipment. typical shutdown current consumption is 40 a at room temperature. optimized for use with small 1 f ceramic capacitors, the adp7104 provides excellent transient performance. shutdown vin gnd en/ uvlo vout r1 r2 1.22v reference vreg pgood pg sense short-circuit, thermal protect 10a 09507-055 figure 59 . fixed output voltage internal block d iagram shutdown vin gnd en/ uvlo vout r2 1.22v reference vreg pgood pg adj short-circuit, thermal protect 10a 09507-056 figure 60 . adjustable output voltage internal block diagram internally, the adp7104 consists of a reference, an error amplifier, a feedback voltage divider, and a pmos pass tr ansistor. output current is delivered via the pmos pass device, which is controlled by the error amplifier. the error amplifier compares the reference voltage with the feedback voltage from the output and amplifies the difference. if the feedback voltage i s lower than the reference voltage, the gate of the pmos device is pulled lower, allowing more current to pass and increasing the output voltage. if the feedback voltage is higher than the reference voltage, the gate of the pmos device is pulled higher, allowing less current to pass and decreasing the output voltage. the adp7104 is available in seven fixed output voltage options, ranging from 1. 5 v to 9 v and in an adjustable version with an output voltage t hat can be set to between 1.22 v and 19 v by an external voltage divider. the output voltage can be set according to the following equation: v out = 1.22 v(1 + r1 / r2 ) v out = 5v v in = 8v pg vout vin pg gnd adj en/ uvlo rpg 100k? r4 100k ? r3 100k ? cout 1f cin 1f on off r2 13k? + + r1 40.2k? 09507-075 figure 61 . typical adjustable output voltage application schema tic the value of r2 should be less than 200 k to minimize errors in the output voltage caused by the adj pin input current. for example, when r1 and r2 each equal 200 k , the output voltage is 2.44 v. the output voltage error introduced by the adj pin input current is 2 mv or 0.08%, assuming a typical adj pin input current of 10 na at 25 c. the adp7104 uses the en/uvlo pin to enable and disable the vout pin under normal operating conditions. when en/uvlo is high, vout turns on, when en i s low, vout turns off. for automatic startup, en/uvlo can be tied to vin. the adp7104 incorporates reverse current protections circuitry that prevents current flow backward s through the pass element when the o utput voltage is greater than the input voltage. a comparator senses the difference between the input and output voltages. when the difference between the input voltage and output voltage exceeds 55 mv, the body of the pfet is switched to v out and turned o ff or opened. in other words, the gate is connected to vout .
data sheet adp7104 rev. b | page 17 of 28 applications informa tion capacitor selection output capacitor the adp7104 is designed for operation with small, space - saving ceramic capacitors but functions with most commonly used capacitors as long as care is taken with regard to the effective series resistance (esr) value. the esr of the output capacitor affects the stability of the ldo control loop. a minimum of 1 f capacitance with an esr o f 1 ? or less is recommended to ensure the stability of the adp7104 . transient response to changes in load current is also affected by output capacitance. using a larger value of output capacitance improves th e transient response of the adp7104 to large changes in load current. figure 62 shows the transient responses for an output capacitance value of 1 f. ch2 50mv ch1 500ma m 20 s a ch1 270m a 1 2 t 10% ? load current output voltage 09507-057 figure 62 . output transient response, v out = 1.8 v, c out = 1 f input bypass capacitor connecting a 1 f capacitor from vin to gnd reduces the circuit sensitivity to printed circuit board (pcb) layout, especially when long input traces or high source impedanc e are encountered. if greater than 1 f of output capacitance is required, the input capacitor should be increased to match it. input and output capacitor properties any good quality ceramic capacitors can be used with the adp7104 , as long as they meet the minimum capacitance and maximum esr requirements. ceramic capacitors are manufac - tured with a variety of dielectrics, each with different behavior over temperature and applied voltage. capacitors must have a dielectric adequate to ensure the minimum capacitance over the necessary temperature range and dc bias conditions. x5r or x7r dielectrics with a voltage rating of 6.3 v to 25 v are recommended. y5v and z5u dielectrics are not recommended, due to their p oor temperature and dc bias characteristics. figure 63 depicts the capacitance vs. voltage bias characteristic of an 0402, 1 f , 10 v, x5r capacitor. the voltage stability of a capacitor is strongly influenced by the capacitor size and voltage rating. in general, a capacitor in a larger package or higher voltage rating exhibits better stability. the temperature varia tion of the x5r dielectric is ~ 15% over the ?40c to +85 c temperature range and is not a function of package or voltage rating. 1.2 1.0 0.8 0.6 0.4 0.2 0 0 2 4 6 8 10 ca p aci t ance (f) volt age (v) 09507-058 figure 63 . capacitance vs. voltage characteristic use equation 1 to determine the worst - case capacitance accounting for capacitor variation over temperature, component tolerance, and voltage. c eff = c bias (1 ? t empco ) (1 ? tol ) (1) where: c bias is the effective capacitance at the operating voltage. tempco is the worst - case capacitor temperature coefficient. tol is the worst - case component tolerance. in this example, the worst - case temperature coefficient (tempc o) over ?40 c to +85 c is assumed to be 15% for an x5r dielectric . the tolerance of the capacitor (tol) is assumed to be 10%, and c bias is 0.94 f at 1.8 v, as shown in figure 63. substituting these values in equation 1 yields c e ff = 0.94 f (1 ? 0.15) (1 ? 0.1) = 0.719 f therefore, the capacitor chosen in this example meets the minimum capacitance requirement of the ldo overtemper - ature and tolerance at the chosen output voltage. to guarantee the performance of the adp7104 , it is imperative that the effects of dc bias, temperature, and tolerances on the behavior of the capacitors be evaluated for each application.
adp7104 data sheet rev. b | page 18 of 28 programable undervoltage l ockout (uvlo ) the adp7104 uses the en/uvlo pin to enable and disable the vout pin under normal operating conditions. as shown in figure 64 , when a rising voltage on en crosses the upper threshold, vout turns on. when a falli ng voltage on en/ uvlo crosses the lower threshold, vout turns off. the hysteresis of the en/uvlo threshold is determined by the thevenin equivalent resistance in series with the en/ uvlo pin. 2.0 1.8 1.6 1.4 1.2 1.0 0.8 0.6 0.4 0.2 1.25 1.50 1.75 2.00 2.25 2.50 2.75 3.00 1.00 0 v out , en rise v out , en f al l 09507-060 figure 64 . typical vout response to en pin operation the upper and lower thresholds are user programmable and can be set using two resistors. when the en/uvlo pin voltage is below 1.22 v, the ldo is disabled. when the en/uvlo pin voltage transitions above 1.22 v, the ldo is enabled and 10 a hysteresis current is sourced out the pin raising the voltage, thus providing threshold hysteresis. typically, two external resistors program the minimum operational voltage for the ldo. the resistance values, r 1 and r 2 can be determined from: r1 = v hys / 10 a r2 = 1.22 v r1 /( v in ? 1.22 v) where: v in is the desired turn - on voltage. v hys is the desired en/uvlo hysteresis level. hysteresis can also be achieved by connecting a resistor in series with en/uvlo pin. for the example shown in figure 65, the e nable threshold is 2.44 v with a hysteresis of 1 v. v out = 5v v in = 8v pg vout vin pg gnd sense en/ uvlo 100k ? 100k ? 100k ? cout 1f cin 1f on off + + 09507-059 figure 65 . typical en pin voltage divider figure 64 shows the typical hysteresis of the en/uvlo pin. this prevents on/off oscil lations that can occur due to noise on the en pin as it passes through the threshold points. the adp7104 uses an internal soft - start to limit the inrush current when the output is enabled. the start - up time for the 3.3 v option is approximately 580 s from the time the en active threshold is crossed to when the output reaches 90% of its final value. as shown in figure 66 , the start - up time is dependent on the output voltage setting . time (s) 0 500 1000 1500 2000 6 4 5 3 2 1 0 v out (v) 5v 3.3v enable 09507-061 figure 66 . typical start - up behavior
data sheet adp7104 rev. b | page 19 of 28 power - good feature the adp7104 provides a power - good pin ( pg ) to indicate the status of the output. this open - drain output requires an externa l pull - up resistor to vin. if the part is in shutdown mode, current - limit mode, or thermal shutdown, or if it falls below 90% of the nominal output voltage, the power - good pin (pg) immediately transitions low. during soft - start, the rising threshold of the power - good signal is 93.5% of the nominal output voltage. the open - drain output is held low when the adp7104 has suffi - cient input voltage to turn on the internal pg transistor. the pg transistor is terminate d via a pull - up resistor to vout or vin. power - good accuracy is 93.5% of the nominal regulator output voltage when this voltage is rising, with a 90% trip point when this voltage is falling. regulator input voltage brownouts or glitches trigger power no g ood signals if v out falls below 90% . a normal power - down causes the power - good signal to go low when v out drops below 90% . figure 67 and figure 68 show the typical power - good rising and falling threshol d over temperature. 0 1 2 3 4 5 6 4.2 4.3 4.4 4.5 4.6 4.7 4.8 4.9 5.0 pg (v) v out (v) pg ?4 0 c pg ? 5 c pg +2 5 c pg +8 5 c pg +12 5 c 09507-062 figure 67 . typical power - good threshold vs . temperature, v out rising 0 1 2 3 4 5 6 4.2 4.3 4.4 4.5 4.6 4.7 4.8 4.9 5.0 pg (v) v out (v) pg ?4 0 c pg ? 5 c pg +2 5 c pg +8 5 c pg +12 5 c 09507-063 figure 68 . typical power - good threshold vs . temperature, v out falling n oise r eduction of the a djustable adp7104 the ultralow output noise of the fixed output adp7104 is achieved by keeping the ldo error amplifier in unity gain and setting the reference voltage equal to the output voltage. this architecture does not work for an adjustable output voltage ldo. the adjustable output adp7104 uses the more conventional architecture where the reference voltage is fixed and the error a mplifier gain is a function of the output voltage. the disadvantage of the conventional ldo architecture is that the output voltage noise is proportional to the output voltage. the adjustable ldo circuit may be modified slightly to reduce the output voltag e noise to levels close to that of the fixed output adp7104 . the circuit shown in figure 69 adds two additional components to the output voltage setting resistor divider. c nr and r nr are added in parallel with r fb1 to reduce the ac gain of the error amplifier. r nr is chosen to be equal to r fb2 , this limits the ac gain of the error amplifier to approxi - mately 6 db. the actual gain is the parallel combination of r nr and r fb1 divided by r fb2 . this ensures that the error amplifier always operates at greater than unity gain. c nr is chosen by setting the reactance of c nr equal to r fb1 ? r nr at a frequency between 50 hz and 100 hz. this sets the frequency where the ac gain of the error amplifier is 3 db down from its dc gain. v out = 5v v in = 8v pg vout vin pg gnd adj en/ uvlo 100k? 100k ? 100k ? cout 1f cin 1f on off r nr 13k ? r fb2 13k ? + + r fb1 40.2k ? c nr 100nf + 09507-064 figure 69 . noise reduction modification to adjustable ldo the noise of the ldo is ap proximately the noise of the fixed output ldo (typically 15 v rms) times the square root of the parallel combination of r nr and r fb1 divided by r fb2 . based on the component values shown in figure 69 , the adp7104 has the following characteristics: x dc gain of 4.09 ( 12.2 db) x 3 db roll off frequency of 59 hz x high frequency ac gain of 1.82 ( 5.19 db) x noise reduction factor of 1.35 ( 2.59 db) x rms noise of the adjustable ldo without noise red uction of 27.8 v rms x rms noise of the adjustable ldo with noise reduc - tion (assuming 15 v rms for fixed voltage option) of 20.25 v rms
adp7104 data sheet rev. b | page 20 of 28 current limit and th ermal overload protection the adp7104 is protect ed against damage due to excessive power dissipation by current and thermal overload protection circuits. the adp7104 is designed to current limit when the output load reaches 6 00 ma (typical). when the output load exceeds 6 00 ma, the output voltage is reduced to maintain a constant current limit. thermal overload protection is included, which limits the junction temperature to a maximum of 150c (typical). under extreme conditions (that is, high ambient temper ature and/or high power dissipation) when the junction temperature starts to rise above 150c, the output is turned off, reducing the output current to zero. when the junction temperature drops below 135c, the output is turned on again, and output current is restored to its operating value. consider the case where a hard short from vout to ground occurs. at first, the adp7104 current limits, so that only 6 00 ma is co nducted into the short. if self heating of t he junction is great enough to cause its temperature to rise above 150c, thermal s hutdown activates, turning off the output and reducing the output current to zero. as the junction temperature cools and drops below 135c, the output turns on and conducts 6 00 ma into the short, again causing the junction temperature to rise above 150c. this thermal oscillation between 135c and 150c causes a current oscillation between 6 00 ma and 0 ma that continues as long as the short remains at the outpu t. current and thermal limit protections are intended to protect the device against accidental overload conditions. for reliable operation, device power dissipation must be externally limited so the junction temperature does not exceed 125 c. thermal consideratio ns in ap plications with low input - to - output voltage differential, the adp7104 does not dissipate much heat. however, in applications with high ambient temperature and/or high input voltage , the heat dissipated in the package may become large enough that it cause s the junction temperature of the die to exceed the maximum junction temperature of 125 c. when the junction temperature exceeds 150c, the converter enters thermal shutdown. it recovers only after the juncti on temper ature has decreased below 135c to prevent any permanent damage. therefore, thermal analysis for the chosen application is very important to guarantee reliable performance over all conditions. the junction temperature of the die is the sum of the ambient temperature of the environment and the tempera - ture rise of the package due to the power dissipation, as shown in equation 2 . to guarantee reliable operation, the junction temperature of the adp7104 must not exceed 125c. to ensure that the junction temperature stays below this maximum value, the user must be aware of the parameters that contribute to junction temperature changes. these parameters include ambient temperature , power dissipation in the power device, a nd thermal resistances between the junction and ambient air ( ja ). the ja number is dependent on the package assembly compounds that are used and the amount of copper used to solder the package gnd pins to the pcb. table 6 shows typical ja v alues of the 8 - lead soic and 8 - l ead lfcsp package s for various pcb copper sizes. table 7 shows the typical jb values of the 8 - lead soic and 8 - l e a d l f c s p. table 6 . typical ja values co pper size (mm 2 ) ja (c/w) lfcsp soic 25 1 165.1 167.8 100 125.8 111 500 68.1 65.9 1000 56.4 56.1 6400 42.1 45.8 1 device soldered to minimum size pin traces. table 7 . typical jb values model jb (c/w) lfcsp 15.1 soic 31. 3 the junction temperature of the adp7104 is calculated from the following equation: t j = t a + ( p d ja ) (2) where: t a is the ambient temperature. p d is the power dissipation in the die, given by p d = [( v in ? v out ) i load ] + ( v in i gnd ) (3) where: i load is the load current. i gnd is the ground current. v in and v out are input and output voltages, respectively. power dissipation due to ground current is quite small and can be ignored. therefore, the junction t emperature equation simplifies to the following: t j = t a + {[( v in ? v out ) i load ] ja } (4) as shown in equation 4, for a given ambient temperature , input - to - output voltage differential, and continuous load current, there exists a minimum copper size re quirement for the pcb to ensure that the junction temperature does not rise above 125c. figure 70 to figure 77 show junction temperature calculations for different ambient temperatures, power dissipat ion, and areas of pcb copper.
data sheet adp7104 rev. b | page 21 of 28 25 35 45 55 65 75 85 95 105 1 15 125 135 145 0 0.2 0.4 0.6 0.8 1.0 1.2 1.4 1.6 1.8 2.0 2.2 2.4 junction temper a ture (c) t ot al power dissi pa tion (w) 6400mm 2 500mm 2 25mm 2 t j max 09507-065 figure 70 . lfcsp, t a = 25c junction temper a ture (c) 50 60 70 80 90 100 1 10 120 130 140 0 0.2 0.4 0.6 0.8 1.0 1.2 1.4 1.6 1.8 t ot al power dissi pa tion (w) 6400mm 2 500mm 2 25mm 2 t j max 09507-066 figure 71 . lfcsp, t a = 50c junction temper a ture (c) 65 75 85 95 105 1 15 125 135 145 0 0.1 0.2 0.3 0.4 0.5 0.6 0.7 0.8 0.9 1.0 t ot al power dissi pa tion (w) 6400mm 2 500mm 2 25mm 2 t j max 09507-067 figure 72 . lfcsp, t a = 85c 25 35 45 55 65 75 85 95 105 1 15 125 135 145 0 0.2 0.4 0.6 0.8 1.0 1.2 1.4 1.6 1.8 2.0 2.2 2.4 t ot al power dissi pa tion (w) junction temper a ture (c) 6400mm 2 500mm 2 25mm 2 t j max 09507-068 figure 73 . soic, t a = 25c 50 60 70 80 90 100 1 10 120 130 140 0 0.2 0.4 0.6 0.8 1.0 1.2 1.4 1.6 1.8 t ot al power dissi pa tion (w) junction temper a ture (c) 6400mm 2 500mm 2 25mm 2 t j max 09507-069 figure 74 . soic, t a = 50c 65 75 85 95 105 1 15 125 135 145 0 0.1 0.2 0.3 0.4 0.5 0.6 0.7 0.8 0.9 1.0 t ot al power dissi pa tion (w) junction temper a ture (c) 6400mm 2 500mm 2 25mm 2 t j max 09507-070 figure 75 . soic, t a = 85c
adp7104 data sheet rev. b | page 22 of 28 in the case where the board temperature is known, use the thermal characterization parameter, jb , to estimate the junction temperature rise ( see figure 76 and figure 77 ). maximum junction temperature (t j ) is calculated from the board temperature (t b ) and power dissipation (p d ) using the following formula: t j = t b + ( p d jb ) (5) the typic al value of jb is 15.1c/w for the 8 - lead lfcsp package and 31.3c/w for the 8 - lead soic package. t ot al power dissi pa tion (w) junction temper a ture (t j ) 0 20 40 60 80 100 120 140 0 0.5 1.0 1.5 2.0 2.5 3.0 3.5 4.0 4.5 5.0 5.5 6.0 6.5 7.0 t b = 25c t b = 50c t b = 65c t b = 85c t j max 09506-071 figure 76 . lfcsp t ot al power dissi pa tion (w) junction temper a ture (t j ) 0 20 40 60 80 100 120 140 0 0.5 1.0 1.5 2.0 2.5 3.0 3.5 t b = 25c t b = 50c t b = 65c t b = 85c t j max 09507-072 figure 77 . soic
data sheet adp7104 rev. b | page 23 of 28 printed circuit b oard layout consideration s heat dissipation from the package can be improved by increasing the amount of copper attached to the pins of the adp7104 . however, as listed in table 6 , a point of diminishing returns is eventually reac hed, beyond which an increas e in the co pper size does not yield significant heat dissipation benefits . place t he input capacitor as close as possible to the v in and gnd pins. place t he output capacitor as close as possible to the v out and gnd pins . use of 0805 or 0603 size capacitors and resistors achieve s the smallest possible footprint solution on boards where area is limited . 09507-073 figure 78 . example lfcsp pcb layout 09507-074 figure 79 . example soic pcb layout
adp7104 data sheet rev. b | page 24 of 28 ou tline dimensions 1 12008- a pin 1 indic a t or (r 0.2) exposed p ad bot t om view t op view 1 4 8 5 index are a 3.00 bsc sq sea ting plane 0.80 0.75 0.70 0.30 0.25 0.18 0.05 max 0.02 nom 0.80 max 0.55 nom 0.20 ref 0.50 bsc coplanarity 0.08 2.48 2.38 2.23 1.74 1.64 1.49 0.50 0.40 0.30 compliant to jedec standards mo-229-weed-4 for proper connection of the exposed pad, refer to the pin configuration and function descriptions section of this data sheet. figure 80 . 8 - lead lead frame chip scale package [lfcsp_wd] 3 mm 3 mm body, very very thin, dual lead (cp - 8 - 5) dimensions shown in millimeters compliant t o jedec s t andards ms-012-a a 06-03-20 1 1-b 1.27 0.40 1.75 1.35 2.41 0.356 0.457 4.00 3.90 3.80 6.20 6.00 5.80 5.00 4.90 4.80 0.10 max 0.05 nom 3.81 ref 0.25 0.17 8 0 0.50 0.25 45 coplanarit y 0.10 1.04 ref 8 1 4 5 1.27 bsc sea ting plane for proper connection of the exposed pad, refer to the pin configuration and function descriptions section of this data sheet. bot t om view top view 0.51 0.31 1.65 1.25 3.098 figure 81 . 8 - lead standard small outline package, with exposed pad [soic_n_ep] narrow body (rd - 8- 2) dimensions shown in millimeters
data sheet adp7104 rev. b | page 25 of 28 ordering guide model 1 temperature range output voltage (v) 2 , 3 package description package option branding adp 7104 acpz -r 7 ? 40 c to + 125 c adjustable 8 - lead l fcsp _wd cp -8 -5 lh1 adp 7104 acpz - 1.5 -r 7 ? 40 c to + 125 c 1.5 8 - lead lfcsp_wd cp -8 -5 lk 6 adp 7104 acpz - 1.8 -r 7 ? 40 c to + 125 c 1.8 8 - lead lfcsp_wd cp -8 -5 lk 7 adp 7104 acpz - 2.5 -r 7 ? 40 c to + 125 c 2.5 8 - lead lfcsp_wd cp -8 -5 lkj adp 7104 acpz - 3.0 -r 7 ? 40 c to + 125 c 3.0 8 - lead lfcsp_wd cp -8 -5 lkk adp 7104 acpz - 3.3 -r 7 ? 40 c to + 125 c 3.3 8 - lead lfcsp_wd cp -8 -5 lkl adp 7104 acpz - 5.0 -r 7 ? 40 c to + 125 c 5 8 - lead lfcsp_wd cp -8 -5 lkm adp 7104 acpz - 9.0 -r 7 ? 40 c to + 125 c 9 8 - lead lfcsp_wd cp -8 -5 lld adp 7104 ardz -r 7 ? 40c to +12 5 c adjustable 8 - lead soic_n_ep rd -8 -2 adp 7104 ardz - 1.5 - r 7 ? 40 c to + 125 c 1.5 8 - lead soic_n_ep rd - 8 - 2 adp 7104 ardz - 1.8 -r 7 ? 40 c to + 125 c 1.8 8 - lead soic_n_ep rd -8 -2 adp7104ardz - 2.5 -r 7 ? 40 c to + 125 c 2.5 8 - lead soic_n_ep rd -8 -2 adp 7104 ardz - 3.0 -r 7 ? 40 c to + 125 c 3.0 8 - lead soic_n_ep rd -8 -2 adp 7104 ardz - 3.3 -r 7 ? 40 c to + 125 c 3.3 8 - lead soic_n_ep rd -8 -2 adp 7104 ardz - 5.0 -r 7 ? 40 c to + 125 c 5 8 - lead soic_n_ep rd -8 -2 adp 7104 ardz - 9.0 -r 7 ? 40 c to + 125 c 9 8 - lead soic_n_ep rd -8 -2 adp 7104cp - evalz 3.3 lfcsp evaluation board adp 7104rd - evalz 3.3 soic evaluation board adp 7104 cpz - redykit lfcsp redykit adp 7104 rdz - redykit soic redykit 1 z = rohs compliant part. 2 for additional voltage options, contact a local analog devices, inc., sales or distribution representative . 3 the adp710 4 cp - evalz and adp710 4 rd - evalz evaluation boards are preconfigured with a 3.3 v adp7104 .
adp7104 data sheet rev. b | page 26 of 28 notes
data sheet adp7104 rev. b | page 27 of 28 notes
adp7104 data sheet rev. b | page 28 of 28 notes ? 2011 C 2012 analog devices, inc. all rights reserve d. trademarks and registered trademarks are the property of their respective owners. d09507 - 0- 3/12(b)

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